[time-nuts] Frequency counter questions

Hal Murray hmurray at megapathdsl.net
Mon Apr 24 18:54:39 EDT 2017

kb8tq at n1k.org said:
> You have a “gate” from the GPSDO and a “signal” from somewhere else. If you
> want the STM to do the whole thing, the “gate” pin needs to get the job done
> in  X +/-  1 cycles of the “signal” pin. Delay X (if it’s consistent) isn’t
> a problem. Having a
> +/- 1 cycle delay *is* a problem. The interrupt servicing structure in the
> MCU may or may not be able to hit things +/- 10 ns or even +/- 100 ns.
> Sometimes a “lower power” MCU with simple code is better at this than a
> multi core gizmo running a high level operating system.  

Some of the counter/timer hardware has another register where the hardware 
will save a copy of the main counter when another signal happens.  If your 
gate time is the time between two pulses rather than the width of a single 
pulse, then all the software has to do is read that copy-register before the 
next pulse happens.

These are my opinions.  I hate spam.

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