[time-nuts] Sub-ps delay line

Scott Stobbe scott.j.stobbe at gmail.com
Tue Feb 7 12:21:43 EST 2017

I would also advise you take a look at how well you can maintain your
system impedance, say 50 Ohms. For example, I have seen about 100's ps
phase difference on a 10 MHz reference, using one BNC female-female coupler
versus another, a small part is due to TOF, but most of that is due to
subtle differences in the impedance of each coupler, thus by causing
reflections. The same is true for one cable versus another.

On Tue, Feb 7, 2017 at 11:13 AM, Mattia Rizzi <mattia.rizzi at gmail.com>

> Hello,
> I'm looking/designing a sub-ps delay line with very high stability.
> Basically it has microwave requirements on phase matching.
> The main features that such delay line should have are:
> - sub-ps resolution and about 1 ns range
> - High stability, must not drift more than 2ps/year, preferably 1ps/year
> - Temperature coefficient (tempco) below 1 ps/celsius
> - Low phase noise floor, target random jitter below 100 fs RSM from 100Hz
> to 1MHz.
> - flicker noise below -90dBc at 1Hz (100MHz carrier)
> - cheap (below 50 euros) and PCB integrable
> - optional: autocalibration or a way to check calibration health over time
> (checking the oscillation frequency of the delay line connected as loop?)
> Operating conditions: The delay line will be used for RF distribution,
> where the clock signals (100-200MHz) must stay in +/- 10 ps error window.
> Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
> accurate, with maximum of +/- 3ps of delay uncertainty. The delay line is
> used to phase-match the  clock outputs at factory, hence will not be
> anymore modified (or for only fine corrections, tens of picoseconds). The
> factory calibration compensates for the delay line and PCB
> process/production variations. The boards will operate at almost same
> temperature and humidity levels over years of continuous running.
> Circuit constrains: The delay line is fed with an AC-coupled LVPECL clock
> output (only P output used) and should provides a single-ended AC clock
> output signal.
> Indeed, no commercial chip fits into these requirements.
> My idea is to use an RC filter to delay the input clock signal and then to
> restore the clock edges with a LTC6957-1 (LVPECL outputs).
> The RC filter would be realized using a varactor (Skyworks SMVA1470-004LF)
> and a 16-bit DAC to control the voltage bias (+ stable voltage reference).
> I already checked the values, and sub-ps resolution seems easily
> achievable. The solution requires a factory calibration due to the
> non-linear behavior of the varactor, but since I only need small
> adjustments, this is not a problem.
> The problem is to guarantee the calibration over years of operation.
> Since a femtofarad parasitic capacitance can change the delay, I already
> thought about protecting the delay line with some kind of resin (Epoxy?)
> and/or a RF cage to protect it from dirt and moisture.
> One of the issue is aging. I derived a typical varactor aging from VCTCXO
> oscillators (no varactor manufacturer knows the effects of aging on its
> products, apparently) and it's still good. But the aging of LTC6957 is not
> known.
> Is the PCB fabrication using microwave requirements on the dielectric fine?
> Based on your experience, do you think that such delay line can respect the
> requirements listed above, especially stability?
> Am I missing something?
> Thank you!
> cheers,
> Mattia Rizzi
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