[time-nuts] PLL performance?

Attila Kinali attila at kinali.ch
Tue Mar 21 07:26:59 EDT 2017


On Mon, 20 Mar 2017 21:07:03 -0400
David Scott Coburn <scotttt at optonline.net> wrote:

> I have built and tested a PLL circuit that will be used to generate a 1 MHz
> signal locked to a 0.5 HZ signal from a pendulum.  (Details available upon
> request.)
> I tested this by feeding the 0.5 Hz output of the PLL into a "time-stamp
> counter" board which I built to go into an HP 3582A Data Acquisition unit.
>  The TSC uses the 5 MHz signal from the HP 107A to feed a free-running 32-bit
> binary counter.  The 0.5 Hz input latches the count value (on the rising edge
> of the signal), which is then logged.

The VCO in the 4046 is an odd mixture between a relaxation and an
delay line oscillator. It's stability is not that good (at least
not by modern standards). As such, your phase comparator frequency
of just 0.5Hz is too low for the 4046 to show its peak performance,
as it is basically free running for 2s before a slight correction
is applied. Usually the frequencies used for a 4046 are in the range
of 1kHz to 100kHz.

Alternatively, you can dissable the internal VCO (inhibit pin) and
use an external oscillator that is more stable. The VCXOs by Abracon
(ASVTX-*) are readily available and cheap enough. If you use a 20MHz
oscillator (e.g. ASVTX-09-20) divide the output first by 2 (using a 
D-flipflop) and then by 10 (e.g. using 74LV161)
until you are at 1Hz, then use second D-flipflops to get to 0.5Hz.
This gives you 1MHz inbetween.
> The standard deviation for the data is about 55 counts.

This means that your jitter (at 0.5Hz) is 11┬Ás RMS.
> The plot looks to my eye to be a nice Gaussian shape, so I assume that the 
> deviations are caused mainly by (white?) noise.  There does not look to be 
> much other structure in the shape of the data.  (Comments welcome.)

Yes, It looks very much Gauss shaped, it is very likely that this is
indeed a Gauss process, but to be sure (in a statistical sense) you
would need to do something like a qq-plot or similar to check,
whether it's actually a Gaus distribution (there are others that
look very similar). But for all practical purposes, that does not
really matter.

Please be aware that a noise process can be Gaussian and not be white.
E.g. 1/f-noise has a Gaussian distribution as well.

> I have looked for information on the web about others who may have done this 
> kind of PLL, but did not find much.
> Does anyone know of any articles related to this?

What information are you looking for?

> If so, do you know what kind of performance they got?

Your performance seem's ok, but limited by the VCO of the 4046.

As your PLL frequency is very very low, you will face a lot of
difficulties due to leakage and other non-idealities of the
various components. I would recommend to use a digital PLL 
implemented in a uC (PIC, AVR32, ARM Cortex-M0/M3) instead.
If you clock the uC from the 1MHz signal and use the 
capture/compare (aka timer) unit of the uC will give you
a resolution in the region of 10-40ns, which should be good
enough considering the noise/stability of the pendulum.
With that you can easily implement a PLL with a loop time constant
of several seconds without the fear of running into problems from
the analog parts.

				Attila Kinali

It is upon moral qualities that a society is ultimately founded. All 
the prosperity and technological sophistication in the world is of no 
use without that foundation.
                 -- Miss Matheson, The Diamond Age, Neil Stephenson

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