[time-nuts] PLL Digital Loop Filter
kb8tq at n1k.org
Tue Mar 21 21:45:24 EDT 2017
Some quick hints:
1) You need a way to digitize the phase input with adequate resolution. If you have a 1 second period and want
1 ns, you need a way to digitize at a 1:1,000,000,000 sort of level. That’s in the 30 bit range so a simple ADC
isn’t going to do it alone.
2) You need a way to digitize the control output. If you have a +/- 2 ppm EFC range and a 16 bit DAC you get
a LSB step around 4/65,000 = 6x10^-8. If you are after < 1x10^-9, 16 bits isn’t going to get you there all by it’s
3) In the middle of the two, you have a loop gain, an integrator time constant, and a bit of phase shift. That plugs
into the standard equations to come up with a solution (along with the normal sensitivities that drive any PLL).
Yes, there are a lot of weird issues to deal with, but conceptually there isn not a lot to it.
> On Mar 21, 2017, at 7:25 PM, James Peroulas <james at peroulas.com> wrote:
> Thanks for the hints and references everyone. I'll dig in and possibly come
> back with some more questions.
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