[time-nuts] Single ended or differential input to TDC chip

David davidwhess at gmail.com
Tue Mar 28 07:10:45 EDT 2017

On Mon, 27 Mar 2017 18:05:13 +0200, you wrote:

>* Single-ended input in a chip might lead to shifting ground potential
>  on the chip and thus to measurment jitter.

This is a major problem I have run across before.  Various single
ended logic families have great noise immunity as far as proper
functioning but their limited PSRR (power supply rejection ratio)
becomes vary apparent when power supply noise shifts their logic
thresholds resulting in additional jitter.  Depending on the logic
family, single ended inputs may be referenced to one or the other
supply or to both.

For this reason alone I would use differential inputs which can always
be driven single ended in less demanding applications.  Some ECL parts
include a "reference" input/output for their logic inputs and might
also be suitable.

Powering critical logic with a reference grade supply voltage and
avoiding ground loops helps mitigate the effects of poor PSRR.

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