[time-nuts] Input filter for data logger

[Attila Kinali]

On Sun, 19 Nov 2017 16:10:54 -0500
Vlad <time at patoka.org> wrote:

> Here is my schematic:
> 
> http://www.patoka.ca/OCXO/LOGGER/IMG_20171119_155907272.jpg

Ok.. I am surprised, this doesn't oscillate.

You have a two stage amplifier, where the second stage
has a negative feedback path into the first stage.

When a pulse comes in, the jfet will turn on and conduct
current through its drain and source resistors. When the
current reaches something around 6-8mA the pnp will start
conducting. But the collector current of the pnp goes into
the source resistor of the jfet. This will increase the
voltage on the source, thus decreasing the gate-source
voltage, thus turn the jfet off, which in turn will turn
the pnp off, which in then will stop conducting, thus
no current into the source resistor, thus the jfet will
start conducting again... I guess you get it.
 
> I did some simple tests for this. In it seems it was OK up to 10Mhz.
> 
> > But guessing from what you showed, I would say that your amplifier
> > circuit isn't stable and has some gain peaking at around 10MHz.
> > There are two ways to proceed: Either optimize your circuit or
> > simplify it using modern components to the input signal you expect.
> 
> The main purpose for this circuit is to protect the MCU input and make 
> some sine to square conversion.

Use a biased 74AC04. That's the easiest. And you will have very
little noise degradation.

I would think that the MCU can probably take more abuse than the
74AC. Modern ASICs have quite a bit of protection circuits on
their inputs. I am not sure whether the 74-families have seen
upgrades on their protection circuits in the last 30-40 years.

			Attila Kinali


-- 
You know, the very powerful and the very stupid have one thing in common.
They don't alters their views to fit the facts, they alter the facts to
fit the views, which can be uncomfortable if you happen to be one of the
facts that needs altering.  -- The Doctor