[time-nuts] Spice simulation of PSRR and phase noise
attila at kinali.ch
Tue Oct 31 16:26:42 EDT 2017
On Sun, 29 Oct 2017 08:06:37 -0400
Bert Kehren via time-nuts <time-nuts at febo.com> wrote:
> Thank you for posting the link to Richard's excellent paper that does not
> only apply to Cs. In my opinion it is a must read for any one serious in
> doing any work on time and frequency issues.
Well, the way how the HP 5071 synthesis chain is designed is the way
one would do it today. Using SRDs went pretty much out of fashion,
and not only because they are hard to buy these days. Today we have
monolithic VCOs that give 9GHz in a tiny packages with good
phase noise performance. We have PLLs with integrated dividers that
can handle 10GHz inputs with 10MHz references directly. Ie you could
simplify the synthesis chain even further. You could build the complete
synthesis chain for the 5071 on a PCB of 5x5cm and still have space to spare.
Even using a DRO (for lower phase noise) would not make the circuit much bigger.
We kind of live in the golden age of electronics design, even if the constant
shrinking of parts makes them harder to handle for hobbyists.
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use without that foundation.
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