[time-nuts] More on SiLabs 5340
marklgoldberg at gmail.com
Mon Jan 29 18:37:53 EST 2018
Reference my earlier postings titled "SI532X Chips Close In Spurs (Somewhat
Long)". There are many sets of register values that will get you the same
output frequency and the clock builder may not give you an optimal set for
phase noise and spurs. I created a spreadsheet to calculate other sets of
values and chose one that worked the best. I just did it through trial and
error of the different sets of values I came up with until I found one with
On Mon, Jan 29, 2018 at 4:16 PM, John Ackermann N8UR <jra at febo.com> wrote:
> On 01/29/2018 04:54 PM, Chris Caudle wrote:
>> On Mon, January 29, 2018 2:38 pm, John Ackermann N8UR wrote:
>>> The close-in phase noise is quite amazing, but the floor is much worse
>>> than in free-run mode.
>> That phase noise plot doesn't look quite right, what PLL bandwidth did you
> Sorry for the earlier null reply. I just used the settings that the
> ClockBuilder software came up with (which IIRC don't offer any choices
> about loop bandwidth in the "wizard"). I haven't yet dug into the register
> options, but I'm sure that there are ways to optimize.
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