Sun Sep 12 16:34:46 UTC 2010
Initially the output integrator is zero. During the first 50% the error
integrator ramps towards -2,5V.
when switching the switched capacitor to the error integrator at 50% it will
be charged to around -2,5V.
On switching back at the end of the period the switched capacitor is
discharged to the output Integrator
giving near +2,5V.
When reaching steady state I see the following:
The error integrator starts from 0 Volts and ramps down to -1,25V during the
first 50% of the Duty cycle.
(Difference of 5V-2,5V integrated for 50% time). During 50-100% of the duty
cycle the voltage ramps back to 0V.
When having S3 at 50% Duty cycle the switched capacitor is charged quickly
to -1.25V and ramped back
till 100% of the period. Across the 200 Ohms resistor I see a negative
voltage spike of around 900-1000mV
giving a peak current of around -5mA across the switch.
So if I have understood you right your suggestion is to change the PWM for
the switched capacitor
at the first cycle to around the same value as the High PWM and after this
back to a value where the
error integrator is near zero (this will be near 100%).
>>> 5. large negative output spikes on voltage steps>= around 0.5V: When
>>> switching between 2 PWM duty cycle values I see large
>>> negative spikes (up to
>>> negative voltages) on the output voltage. For me it seems
>>> that the input
>>> protection diodes between negative and positive input (1.1V
>>> forward voltage)
>>> are going to be forward biased.
> If the difference in output corresponding to the 2 PWM values is small as
> is almost always the case when the DAC is used to set the EFC voltage of
> the OCXO in a GPSDO or similar control loop such behaviour shouldn't be an
You are right: practically this has nearly no impact. Except when the stage
that follows will
be disturbed by negative voltages one should divide large output steps into
a couple of smaller steps.
With best regards.
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