[volt-nuts] How to keep voltage stable in the sub-100nV range?

[Charles Steinmetz]

Attila wrote:

> I have a "small" side project, which involves keeping a voltage stable
> to better than 100nV over the period of several seconds.
>    *   *   *
> I know the basic literature on noise and how to deal with that.
> What I am interested in are the real world problems, how big
> they actually are and how to deal with them.

Noise is just one of the concerns, and potentially not the hardest one 
to deal with.  Settling time will be a real issue.  If the full-scale 
output is 1v, you need to wait for the system to settle to within nearly 
24 bits.

First, the LP filters will have a prolonged settling tail to 100nV 
(meaning that the basic regulation must show 100nV stability for longer 
-- probably much longer -- than you are contemplating), so drift may be 
much more of an issue than you anticipate.

Second, everything -- the reference, the DAC, the buffer amps, the 
resistors, and even the capacitors -- will exhibit temperature effects. 
  You will need an extremely stable thermal environment.  You will also 
need to deal with changes in the self-heating of the DAC, the 
amplifiers, and the resistors when you change the voltage, which will 
likely produce considerably longer settling tails than the LP filters. 
The wider the range of output voltages, the worse the self-heating 
effects will be.

Of course, having to wait for settling to within 24 bits will put a real 
limit on how fast you can change the voltage (how long you have to wait 
after commanding a change before you can rely on the output voltage). 
And what is the downstream circuitry going to be doing during this 
settling time?  Are you going to need a S&H that can hold to within 
100nV for seconds at a time?

This isn't quite so much of a problem if each step is small, but 
settling to within 24 bits is a pretty big deal even in that case.  And 
probably much slower than you are expecting.

Best regards,

Charles