SDR-1000 Oscillator Performance

I've done some experiments to evaluate the frequency stability and phase noise performance of the FlexRadio Systems SDR-1000 software defined radio.

The SDR-1000 uses an Analog Devices AD9854 direct digital synthesis ("DDS") chip, clocked by a low-jitter Valpey-Fisher 200MHz oscillator. While the V-F oscillator has good phase noise performance, it is not specificed to have exceptional frequency accuracy or stability. However, the SDR-1000 also allows you to use an external reference to drive the DDS. The AD9854 has an internal multiplier that allows the use of external references from 10MHz to 50MHz.

I did a series of tests of the frequency accuracy and stability of the Valpey-Fisher oscillator. In short, its frequency stability after warm-up is certainly adequate for all but very demanding uses, and its frequency offset can easily be nulled using the PowerSDR software's calibration routine.

If you need better frequency performance than the V-F oscillator, you can use an external reference. The obvious idea is use a 10MHz frequency standard, but that has a problem. When you multiply a signal, its phase noise is multiplied as well. Multiplying by 20 (to get from 10MHz to 200MHz) increases phase noise by 26dB. The low phase-noise of the V-F oscillator is one of the keys to the SDR-1000's great performance, and use of a low-frequency external reference can compromise that performance (see my data on SDR-1000 Phase Noise Performance for more details about that).

A way around this is to use a phase locked loop to slave a low-noise oscillator at, say, 100MHz to a high stability oscillator at a lower frequency. The TAPR CT1DMK Reflock-II does just that. Luis Cupido, CT1DMK, conceived the Reflock as a universal frequency lock device; it can be configured to lock virtually any voltage-tuned oscillator to a stable frequency reference.

The Reflock-II is a really versatile device, and it's easy to imagine lots of applications for it. One that came readily to mind was to provide a replacement oscillator for the SDR-1000.

Steve Bible, N7HPR, designed a small daughterboard for the Reflock-II to do just that. It includes a 10MHz TXCO to provide accuracy, and a low jitter VCXO for low phase noise (the VCXO output still needs to be multiplied in the DDS chip, but its higher frequency allows a lower multiplication factor, which minimizes the phase noise degradation).

Here are the results of a similar set of frequency stability tests run on a Reflock-II. Its frequency performance should please all but the most extreme "time nut."

Phase noise is another important factor in the performance of an HF receiver. I recently got a chance to play with an Agilent E5052A Signal Source Analyzer that can do phase noise measurement. I used the E5052A to measure the phase noise performance of the SDR-1000 using its standard internal oscillator, as well as two external references: an HP5065A Rubidium frequency standard at 10MHz (using a multiplication factor of 20 inside the AD9854) and the Reflock-II.

There are a number of reasons why I'm not happy with these results, and I hope to get a chance to rerun them soon. I'm presenting them here for your information, but please don't read too much into them. With that warning given, here are the phase noise measurement results.

I've also done a quick experiment to determine the processing latency of the SDR-1000 software.