[time-nuts] Where does the Z3801A 1 PPS come from?
Bill Jones, K8CU
k8cu at realhamradio.com
Mon Mar 14 18:13:22 EST 2005
> [ snip ]
> > I may have done this and will look for the old data. My
> > understanding was always that the 1 PPS output was
> > tied tightly to the OCXO. I guess I don't buy into the
> > idea that the CPU is generating the 1 PPS on its own.
> That's sure what I would have thought -- unless the CPU is being clocked
> from the OCXO and thus is effectively transferring its stability to the
> 1pps (sort of like your PIC divider). But I suspect it would be hard
> for a CPU doing several tasks to maintain the cycle timing of a
> dedicated divider.
> > To me, 1 ns agreement between two signals suggests
> > it's all hardware-based, not software. But I'd be happy
> > to learn I'm wrong.
John's original question asked if the 1 PPS on the Z3801A output connector
is derived from a simple divider from the 10 MHz signal. The answer is no.
The one PPS from the Oncore receiver goes directly to U32, a Xilinx
programmable gate array. A buffered 10 MHz signal from the oscillator also
goes to this same device. Point your 'scope probe to pin 7 to verify.
The 1 PPS that drives the rear panel connector is sourced from an output pin
on the same gate array at U32.
Perhaps if we think about the programmable gate array as a hardware
component rather than as a software defined function, the close correlation
of the 10 MHz and the Oncore 1 PPS makes more sense. Since the gate array
has a clock, address lines, I/O pins, and normal busy/ready/ signals it
could be mistaken for a uP.
In the case of the Z3801A, perhaps the circuit function is closer to a logic
replacement chip on steroids, especially since there is another true
Motorola uP at U33 that appears to take care of the serial I/O (among many
Bill Jones, K8CU
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