[time-nuts] Linear Interpolator

Stephan Sandenbergh stephan at rrsg.ee.uct.ac.za
Thu Jun 29 07:58:06 EDT 2006

[Magnus Danielson wrote :
I would not do this stuff with a clock lower than 50 MHz today. It is easy
enought to acomplish it. 10 MHz is nice and dandy for reference, but I would
use a low-jitter VCXO and lock it to the 10 MHz and then use that clock for


So you suggest, I take the 10MHz output of my OCXO lock that to a stable
VCXO (say 64MHz as not to be a harmonic multiple of 10MHz) and then clock my
FPGA with the resultant output. Wouldn't I loose the advantage of the
dithering effect? I guess if I have a 1ns resolution interpolator, no
dithering is needed? Is the idea to have a sort of a loop within a loop -
the FPGA follows the OCXO which follows the 1PPS?



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