[time-nuts] Linear Interpolator
cfmd at bredband.net
Thu Jun 29 08:13:30 EDT 2006
From: "Stephan Sandenbergh" <stephan at rrsg.ee.uct.ac.za>
Subject: Re: [time-nuts] Linear Interpolator
Date: Thu, 29 Jun 2006 13:58:06 +0200
Message-ID: <000d01c69b73$489311a0$401c9e89 at Stephan>
> [Magnus Danielson wrote :
> I would not do this stuff with a clock lower than 50 MHz today. It is easy
> enought to acomplish it. 10 MHz is nice and dandy for reference, but I would
> use a low-jitter VCXO and lock it to the 10 MHz and then use that clock for
> So you suggest, I take the 10MHz output of my OCXO lock that to a stable
> VCXO (say 64MHz as not to be a harmonic multiple of 10MHz) and then clock my
> FPGA with the resultant output.
I would rephrase that to say that you should lock your low jitter VCXO (of say
64 MHz) to your stable OCXO (of 10 MHz).
Highest common frequency is 2 MHz (divide by 5 for 10 MHz and divide by 32 for
64 MHz). Apply suitable phase-comparator and loop filter of choice.
What you said could be interprented as locking the 10 MHz OCXO to the 64 MHz
clock, which would be slaving the wrong oscillator of the two.
> Wouldn't I loose the advantage of the dithering effect? I guess if I have a
> 1ns resolution interpolator, no dithering is needed?
Indeed. Instead of averaging out the difference, you get improved single-shot
resolution and have less measurement error noise to clog your other
measurements. Sawtooth-corrections will then certainly be needed to combat the
resolution problem of the PPS itself.
> Is the idea to have a sort of a loop within a loop -
> the FPGA follows the OCXO which follows the 1PPS?
Eh, I didn't say that (I kept my mind in the measurement side of the system),
but you can do that if you want. It will be pretty straight-forward. Update a
DAC to stabilize the OCXO just to keep the balance of the time interval
readings. The time interval measurements is the phase-detector, so loop-filter
needs to be applied accordingly.
Oh, what 64 MHz oscillator do you have?
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