[time-nuts] Of rubidium life and piggy-bank anemia....
magnus at rubidium.dyndns.org
Sat Dec 1 09:36:33 EST 2007
From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
Subject: Re: [time-nuts] Of rubidium life and piggy-bank anemia....
Date: Sun, 02 Dec 2007 01:01:53 +1300
Message-ID: <47514D31.9040602 at xtra.co.nz>
> Poul-Henning Kamp wrote:
> > In message <475137C9.1020105 at xtra.co.nz>, Bruce Griffiths writes:
> >> Poul-Henning Kamp wrote:
> >> Please explain why this doesnt work.
> > I tried it :-)
> Not very effectively.
> > Read up on meta-stability in FPGAs somewhere on the web.
> Explain why??
> If you mean that the asymmetry depends on the input signal transition
> slope then you still dont need a dedicated pair of count latches for
> each input.
> Just a set of flags to indicate from with which channels and slopes the
> latched count is associated with.
It is well established that for FPGAs you want to clock the signal through
two DFFs before using it whenever you handle asynchronous signals or signals
from another clock domain. It is common practice and we also every now and then
see that we indeed get problems when we have missed to use that common
Xilinx Application Note 94 "Metastable Recovery in Virtex-II Pro FPGAs" by
Peter Alfke covers the issue:
You can get away without a double DFF if you consider then next level FF as
the second DFF. Routing delay must be tighter thought. If you are not running
at higher clockrates you can also cheat. However, inside a modern FPGA for the
kind of application we are talking, not adding a second DFF is just plain
It should be noted that the DFFs of FPGAs should not be considered as straight
replacements of their separate CMOS, TTL or ECL sibblings as they have been
designed for a mostly synchronous world.
I would not dream of doing a design without double DFFs for asynchronous
signals unless I was making cleaver use of other DFFs.
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