[time-nuts] Of rubidium life and piggy-bank anemia....
bruce.griffiths at xtra.co.nz
Sat Dec 1 15:34:26 EST 2007
Didier Juges wrote:
> I think there may still be a problem if you only have one counter latch and
> a tag to indicate which input's data is in the latch, aside from
> metastability issues. If two of the signals you want to compare are very
> close in timing, there may not be enough time for the processing logic to
> collect the data from the first pulse before the second one comes along.
> As Poul pointed out, if you compare two GPSDOs that are a few nS apart (or
> less), that puts a new strain on the logic collecting data. If each input
> has its own counter latch and you are measuring PPS signals, you have a
> whole second to process the data.
> I guess there could be an issue with multiple counter latches that
> propagation time within the device may not be the same for all inputs, and
> calibration (and possibly temperature compensation of that delay spread)
> might become necessary?
I forgot to mention a couple of salient points (it was rather late):
1) All the flags mentioned are synchronous being derived from the
synchroniser outputs (one per channel).
2) The register is actually a synchronous FIFO.
The depth of the FIFO (or shift register) can easily be made sufficient
to allow one or more count values per channel to occur before the
processor has to deal with them.
Using a FIFO structure like this means that only one address needs to be
read which can save time.
Propagation delay tempco shouldnt be a significant issue as the
resolution is the resolution is at best 1 counter clock period.
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