[time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?

Bruce Griffiths bruce.griffiths at xtra.co.nz
Wed Dec 12 15:19:12 EST 2007

Luis Cupido wrote:
> Bruce,
>  > No analog filtering of the D flipflop output is required.
> Now you got me lost.
> We were talking about a GPSDO, that is locking
> an VCXO on the GPS time (1pps or else)
> So by the end of it you need an analog
> signal to control the voltage input of the VCXO. Right ?
> Where you get that from ?
> If not by filtering your flip-flop output
> what else you have in between the 1pps and the VCXO ?
> CPU's DAC's ????
Some software, including a sigma delta DAC, the effect of which is no
different, in principle, than the filtering etc required by any of your
phase detector implementations.
The 1 bit phase error samples are processed in software (or hardware
depending on one's inclinations, expertise, etc) in a similar way that
samples from an N (>1) phase detector samples are, to produce a digital
output for a DAC which drives the OCXO EFC input. The only difference is
that a sigma delta DAC is used instead of a conventional DAC.

> if so how does your complexity arguments still apply ?
The interpretation of "complexity " depends on ones background and
The originator of the thread indicated that they had some microprocessor
software experience.
> Luis Cupido
I was trying to tailor the design to the stated strengths of the
originator of the thread.

If one is trying to "squeeze" the ultimate in performance when using a
GPS receiver to discipline an OCXO, then carrier phase measurements
potentially offer much higher performance than can be achieved by using
the PPS output of a typical GPS timing receiver.
However only a few commercially available GPS receivers are suitable for
this application.
The GPS receiver oscillators all have to be phase locked to the OCXO
being disciplined.
This approach has been used in at least one commercially available GPSDOCXO.
In principle a GPS receiver has all the required measurement hardware,
so all that is required are suitable algorithms implemented in either
software running on a DSP, microprocessor, etc, or implemented in
hardware (CPLD etc).


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