[time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?

[Luis Cupido]

Hi Michael,

Yes that may be true (but I did not test any of that...)
Well... with digital prog. logic devices that operate
at similar speed than HC and AC should be true yes.
On the fast CPLDs that run past 300MHz the jitter
should have scale down proportionally (I imagine)
but I have no clue if that is similar, better or still
worst than HC or AC.

Yeap... Nice thing to test
Hummm... I'm still thinking how to test such... :-)

Luis Cupido.
ct1dmk.




michael taylor wrote:
> On Dec 12, 2007 7:33 AM, Luis Cupido <cupido at mail.ua.pt> wrote:
>> Very good, I do respect the usage of a bunch of CMOS/TTL chips if
>> someone doesn't want to spend the
>> effort of learning how to use a CPLD. When it comes to use CPUs for
>> tasks better done by straight logic (and there are many examples
>> out there) then I think it is not the right option.
>> All understood so let's not discuss that any further.
> 
> Bruce also alludes to the higher jitters of CPLD versus Advanced/High
> Speed CMOS logic gates (AC or HC families).
> 
> This has to do with the programmable nature of CPLD / FPGA ICs as I
> understand it.
> Ref: <http://www.febo.com/pipermail/time-nuts/2007-April/025299.html>
> 
> -Michael
> 
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