[time-nuts] Austron PRR-10 GPS discliplined Rb...

[David I. Emery]

On Sun, Jan 28, 2007 at 03:07:23PM +1300, Dr Bruce Griffiths wrote:
> > David
> >
> > I presume that the leading edge of the GPS receiver PPS pulse samples 
> > the DDS phase accumulator register content.
> > This is not possible with most modern DDS chips with integrated DACs, in 
> > which the DDS accumulator or its truncated phase output is not 
> > externally accessible, it cannot be read, nor is there any provision for 
> > capturing the phase at the leading edge of an external signal.
> >
> > However one could always use a gate array to implement the digital part 
> > of a DDS and include a phase capture register.
> > An external DAC (and sine table) would be required to synthesize the 
> > corrected sine wave frequency source output.
> >
> > Bruce


> ADDENDUM
> 
> When sampling the phase accumulator of an NCO with the leading edge of 
> an external signal, first the external signal must be synchronised to 
> the NCO clock using a multistage synchroniser. The synchroniser output 
> has an inherent timing jitter of about 2 clock cycles peak to peak which 
> limits the sampled phase effective resolution. To increase the single 
> shot sampled phase effective resolution, either the NCO clock frequency 
> can be increased, incurring greater power dissipation and cost, or a TDC 
> can be used to measure the synchroniser input output delay and combined 
> with the sampled phase to increase the effective single shot sampled 
> phase resolution without increasing the NCO clock frequency.
> 
> Bruce
> 
> 
> Bruce

	I am curious enough to try to figure this out for the PRR-10.   
It did occur to me that to use the 1 PPS to sample the accumulated phase
register you'd pretty obviously want to do this at well over 100 MHz in
order to get enough resolution (eg lack of quantizing noise) to usefully
track in the 10^12 area (100 MHz is only 10 ns time resolution, after
all).

	This is obviously completely inconsistent with a 20 MHz clocked
system (50 ns per tick), though one with an internal PLL multiplier
might be good enough (easily done in a modern FPGA with these things
internal and 400 or better MHz clocks possible, but doubtful for a mid
90s design).

	There is one obvious alternative - use the DDS to synthesize say
5 or 1 mhz and filter that with analog filtering (crystal filter) and
then use the 1 PPS from the Oncore to sample the 5 or 1 mhz with a fast
sampler (eg your suggestion of a TDC) at the time of the 1 PPS edge.  
This provides whatever resolution the  analog A/D and sampler will do
without all the ramp generator complexity.   And does not involve any
form of synchronizer with its inherent uncertainty window.   (And of
course you then do synchronize the 1 PPS and read the coarse phase bits
from the phase accumulator sampled on the 1 PPS).

-- 
   Dave Emery N1PRE,  die at dieconsulting.com  DIE Consulting, Weston, Mass 02493
"An empty zombie mind with a forlorn barely readable weatherbeaten
'For Rent' sign still vainly flapping outside on the weed encrusted pole - in 
celebration of what could have been, but wasn't and is not to be now either."