[time-nuts] 5 MHZ PIC PPS Divider?

Bruce Griffiths bruce.griffiths at xtra.co.nz
Sat Apr 12 19:56:26 EDT 2008

Bruce Griffiths wrote:
> John
> Since the PIC CLK input to output pin transition delay is relatively 
> large (50ns or more on some datasheets) it is likely to have a 
> relatively large tempco (several hundred ps/C) so this may be the 
> primary limiting factor unless the thermal environment is very stable. A 
> fast external resynchronising flipflop may have a clock to output delay 
> and associated tempco at least 10X lower than this.
> Measuring the PIC clock input to PPS output delay tempco should be 
> relatively easy if its tempco is indeed that large.
> Bruce

If the temperature (of the output devices) were logged along with the 
PPS timing data then calibration of the clock to output transition delay 
should allow an effective improvement of at least a factor of 10 in 
effective delay tempco after correction for temperature fluctuations.


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