[time-nuts] 5 MHZ PIC PPS Divider?

Bruce Griffiths bruce.griffiths at xtra.co.nz
Sat Apr 12 18:57:45 EDT 2008


Since the PIC CLK input to output pin transition delay is relatively 
large (50ns or more on some datasheets) it is likely to have a 
relatively large tempco (several hundred ps/C) so this may be the 
primary limiting factor unless the thermal environment is very stable. A 
fast external resynchronising flipflop may have a clock to output delay 
and associated tempco at least 10X lower than this.

Measuring the PIC clock input to PPS output delay tempco should be 
relatively easy if its tempco is indeed that large.


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