[time-nuts] 5 MHZ PIC PPS Divider?

Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Apr 15 20:54:21 EDT 2008

Stanley Reynolds wrote:
> <snip>
> "Using a ripple counter is a particularly bad idea, guaranteeing reliable 
> sampling is likely to be difficult to impossible unless the counter is 
> capable of reliable operation at several GHz.
> The problem being the ripple clock propagation delay from one flipflop 
> to the next. For this counter the input clock to output transition delay 
> is typically over 4nsec whilst the clock to Q0 delay is about 1.7ns a 
> difference of 2.3 cycles at 1 GHz.
> Bruce"
> Yes but if the PIC controls the counter Hold control you should have more than enough time for the counter to settle on the order of  > .5sec < 1 sec when measuring a PPS signal. The chip cost is abt 8 USD . I was looking at this device because of it's speed and low cost the ripple delay was just a trade off, just as the low speed interface to the PC and limited data collected is a trade off.

You still need a 1GHz synchroniser (ECL dual D flipflop or shift 
register) for reliable operation when using the synchronous hold input 
(dont try using the asynchronous hold function as it is much more 
difficult to get this to work reliably).

Range is only 256 ns so that when testing an oscillator with a 
relatively large instability or frequency offset count wrapping will be 
a problem.


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