[time-nuts] 5 MHZ PIC PPS Divider?

Stanley Reynolds stanley_reynolds at yahoo.com
Tue Apr 15 20:36:22 EDT 2008

"Using a ripple counter is a particularly bad idea, guaranteeing reliable 
sampling is likely to be difficult to impossible unless the counter is 
capable of reliable operation at several GHz.
The problem being the ripple clock propagation delay from one flipflop 
to the next. For this counter the input clock to output transition delay 
is typically over 4nsec whilst the clock to Q0 delay is about 1.7ns a 
difference of 2.3 cycles at 1 GHz.

Yes but if the PIC controls the counter Hold control you should have more than enough time for the counter to settle on the order of  > .5sec < 1 sec when measuring a PPS signal. The chip cost is abt 8 USD . I was looking at this device because of it's speed and low cost the ripple delay was just a trade off, just as the low speed interface to the PC and limited data collected is a trade off.

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