[time-nuts] Phase noise & Jitter
peterawson at earthlink.net
Mon Apr 28 11:12:06 EDT 2008
One effect I have observed on uP clock generators is that
fully differential circuits which utilize the crossover of
complementary signals are capable of lower jitter performance
than single ended circuits. At least 2 performance gains are
1) the effective p-p swings are doubled
2) ground & power supply noise are mostly common mode
& have limited influence on the crossover timing
These circuits tend to operate into controlled, low impedance
loads from controlled, low impedance sources resulting in
reduced ringing & other aberrations.
Lastly, these circuits change state with as little change in
internal operating point(s) as practical, so power supply
current transients are minimal.
Some previous posts have referred to "slope-to-noise" ratio. I
don't know that such a parameter exits, but the concept seems
useful. For digital circuits, it would seem that the potential for
metastability & threshold uncertainty, is reduced when the
slope-to-noise ratio is optimized. I wonder if this concept is,
or can be quantified?
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