[time-nuts] Phase noise & Jitter

Henk ten Pierick henk at deriesp.demon.nl
Mon Apr 28 13:20:17 EDT 2008

Hi Don,

Any comparator or slicer has a noise density and a noise bandwidth.  
The noise value of this slicer is the integral of the noise density  
over the noise bandwidth. The noise bandwidth is the slicer  
bandwidth, not the slicer frequency. Due to the slope, thus the slew  
rate, of the input signal the input noise is converted to jitter.
For digital circuits, the input noise is dependent of the design and  
the process. Logic has about 3dB psrr thus the noise on the supply  
should be low as well. Jitter in logic also depends on product brand.  
Lowest jitter is obtained if there are no other functions in the  
package. Thus requires sometimes re-clocking of the logic output with  
a separate d-ff.


On Apr 28, 2008, at 17:12, Pete wrote:

> Don,
> One effect I have observed on uP clock generators is that
> fully differential circuits which utilize the crossover of
> complementary signals are capable of lower jitter performance
> than single ended circuits. At least 2 performance gains are
> obvious;
> 1) the effective p-p swings are doubled
> 2) ground & power supply noise are mostly common mode
>     & have limited influence on the crossover timing
> These circuits tend to operate into controlled, low impedance
> loads from controlled, low impedance sources resulting in
> reduced ringing & other aberrations.
> Lastly, these circuits change state with as little change in
> internal operating point(s) as practical, so power supply
> current transients are minimal.
> Some previous posts have referred to "slope-to-noise" ratio. I
> don't know that such a parameter exits, but the concept seems
> useful. For digital circuits, it would seem that the potential for
> metastability & threshold uncertainty, is reduced when the
> slope-to-noise ratio is optimized. I wonder if this concept is,
> or can be quantified?
> Pete Rawson
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