[time-nuts] Low phase noise digital divider (in 600MHz to10MHz area)

[Bruce Griffiths]

Anders Time wrote:
> Have been locking around for a good article on how to design a good Low
> phase noise digital divider(in 600MHz to 10MHz area), but the have not found
> any good literature. Today most people talk about regenerative dividers, but
> are a rather complex subject.
> Does anyone have experience in what logic family that have the lowest noise
> TTL, AC, HC, F etc?
> What is the upper limit for ECL diviers? My first idea was to use ECL to
> divide down to 100MHz area and then to use lower noise TTL to go down to
> 10MHz.
> What about edge-conditioning circuit at divider input? Have seen people talk
> about it, but no info what it does?
> Thanks
> Anders
>   
Anders

The upper limit for current ECL dividers is well over 1 GHz.
Theres nothing terribly fancy about the edge conditioning circuit at a
divider input, its just a limiting amplifier or comparator used to
amplify the input signal and reduce the input transition times seen by
the divider.

If you are serious about low noise division dont forget to bandpass
filter the input to the divider and bandpass filter the output of each
divide by 16 followed by another clock shaper.
This process minimises the aliased noise at the divider output.

If you want to use a programmable divider this cascaded divide and
filter technique can become somewhat unwieldy.

F dividers are supposed to be quieter but I havent seen any definitive
measurements comparing like with like.

Bruce