[time-nuts] Frequency divider design critique request

Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Jul 11 22:45:00 EDT 2008


> Magnus
> A minimalist approach for the 5MHz to 10MHz doubler could use a full 
> wave (diode, BJT or JFET) doubler followed by a series tuned 5MHz shunt 
> trap to minimise the 5MHz content in the output.
> If the doubler components were perfectly matched (unlikely) the 
> fundamental trap could be omitted.
> The other harmonics are of little concern as the comparator output is a 
> square wave and the rectified sinewave waveform would produce a duty 
> cycle of around 44% at the comparator output.
> The diode turn on threshold will alter the duty cycle somewhat but it 
> should still be acceptable at least for clocking the flipflops and dividers.
> If desired a threshold feedback loop could be used to stabilise the 
> comparator duty cycle at 50%.
> However such a duty cycle stabiliser only works when the input signal 
> waveform is sinusoidal, rectified sinewave or any other signal with a 
> slow enough slew rate.
> Bruce
Attached circuit schematics illustrate the simple doubler configuration 
I had in mind.

The series tuned shunt traps eliminate Fin and its odd harmonics due to 
diode mismatch and transformer imbalance.
In principle the series tuned shunt traps tuned to the odd harmonics of 
the input frequency can all be replaced by a length of open circuited 
1/4 wave (at Fin) low loss transmission line.
However the 50ns of delay line (required for Fin = 5MHz) takes a lot of 

The circuit driving the 74AC14 illustrates how the doubler output may be 
biased with a dc level of Vcc/2.
In practice either a duty cycle stabilising feedback loop or a pot may 
be used to adjust the output duty cycle to 50%.

A similar circuit can be used to drive a comparator.

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