[time-nuts] Test equipment-level phase noise PLLs
dforbes at dakotacom.net
Tue Jul 22 16:26:10 EDT 2008
Matt Ettus wrote:
> In looking into extremely low phase noise synthesizers, I have come
> across the new HMC700LP4 chip from hittite, which seems to have the
> best figure of merit I have found, -227 dBm/Hz. That gives you
> -107dBc/Hz at 20 kHz offset at 6 GHz according to the datasheets.
> That sounds amazingly good, but my R+S signal generator does better.
> Do they use a different sort of architecture? Do they not use
> conventional dividers? Some other sort of phase detector?
They usually use a microwave mixer heterodyning against a harmonic multiplier
driven by the reference frequency, producing an IF in the 30-50 MHz area. Often
there will be a dual loop PLL to improve performance.
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