[time-nuts] Test equipment-level phase noise PLLs
John Miles
jmiles at pop.net
Tue Jul 22 19:30:00 EDT 2008
I've played with the Hittite chips before and obtained PN results in the
same ballpark (see http://www.ke5fx.com/hpll.htm ), but at 8 GHz rather than
6 GHz. To save further head-scratching, the figure of merit on these chips
works like this:
In-band phase noise in dBc/Hz = FOM + 10*log(Fcomp) + 20*log(N)
This is the best-case noise level that you will get assuming a
perfectly-clean reference and no VCO noise contribution. As usual,
Hittite's less-than-ideal data sheet doesn't make that relationship clear.
Specifically, the 5.8-GHz integer-N plot in figure 1 appear to have been
made with a 50 MHz comparison frequency and N=116. -107 dBc/Hz - 77 - 41
= -225 dBc/Hz.
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