[time-nuts] PLL question

Magnus Danielson magnus at rubidium.dyndns.org
Mon Aug 10 15:56:47 UTC 2009


> There is no need for a phase-frequency detector or any other steering
> mechanism when the frequencies being locked never diverge by more than +/-
> 1
> ppm.  Just use a diode mixer and active LPF, IMHO.

Double Balanced Mixer and active LPF indeed. Considering the cleanness of
the signals, XOR or S-R FF should also be able to pull if off cleanly.

Maybe it's just a biasing issue, that the EFC range is so wide? For slow
PLLs I prefer to bias the active output to nominal +/- 0 ppm adjustment
either as fixed offset or as an adjustable offset. That way the remaining
frequency offset should be pulled in fairly quickly.

For quick PLLs such biasing tricks isn't needed, as the capacitor fairly
quickly gets propper DC bias anyway, so it doesn't become much of an
issue.

Once the PLL has locked, a voltage measurement between the bias level and
integrated level can be done, so that the bias pot can be turned until the
voltage reaches 0 V. That way it is trimmed up for the next start.

Cheers,
Magnus




More information about the time-nuts mailing list