[time-nuts] PLL question

[Ulrich Bangert]

Magnus,

> Indeed, but too narrow pulses may still be a problem. The 
> benefit of a continous signal is that the disturbance can be 
> kept at a high frequency and thus be dampend out and the 
> channel capacity for corrections is maintained high.

I have no clue to what you are refering to. Narrow pulses? What narrow
pulses? Continous signal? What continous signal? The AD9901 circuit uses the
flip-flops only in case that there is still a frequency error between the
inputs. Once this frequency error is removed by the loop the circuit works
as if only the XOR were present. Which makes this circuit exactly an very
intelligent and versatile steering device: Frequency comparator if necessary
and XOR phase comparator if possible. 

> You can do alot of tricks in a CPLD. Getting the basic plot 
> of what is good or bad system design still needs to be sorted 
> out. Not meant as criticism, but just as a kind warning.

Sure! I had better said: Due to the simple design and the very good
performance of this phase/frequency comparator I use it as a standard in all
my PLL designs. Since I usually do not need the high frequency capabilities
of the original AD9901 but need only performance up to a few MHz I do not
buy the original part from AD but have covered the circuit diagram into a
number of cplds. These have proved to work so well in a number of PLLs for
different purposes that I can recommend you to do the same from my very own
experience. 

Best regards
Ulrich   

> -----Ursprungliche Nachricht-----
> Von: time-nuts-bounces at febo.com 
> [mailto:time-nuts-bounces at febo.com] Im Auftrag von Magnus Danielson
> Gesendet: Montag, 10. August 2009 15:13
> An: Discussion of precise time and frequency measurement
> Betreff: Re: [time-nuts] PLL question
> 
> 
> >> ...I must admit, the tri-state PC did look good
> >> too until you pointed out the dead zone. I had assumed 
> this would be 
> >> insignificant, but of course it can't be. I'll still try the 
> >> 74HC7046, but use the XOR PC instead.
> >
> > How about switching between the 4046's phase detectors, 
> once the PLL 
> > has locked?
> 
> You can do that, the PFD lock detect could be used to let a 
> CMOS analog gate switch over.
> 
> > Or using a phase comparator like the AD9901 which has a "no 
> dead zone" 
> > XOR phase comparator coupled with a frequency comparator?
> 
> Indeed, but too narrow pulses may still be a problem. The 
> benefit of a continous signal is that the disturbance can be 
> kept at a high frequency and thus be dampend out and the 
> channel capacity for corrections is maintained high.
> 
> > The later one can easily be put into a small cpld if you like.
> 
> You can do alot of tricks in a CPLD. Getting the basic plot 
> of what is good or bad system design still needs to be sorted 
> out. Not meant as criticism, but just as a kind warning.
> 
> Cheers,
> Magnus
> 
> 
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