[time-nuts] time-nuts Digest, Vol 56, Issue 71
Tom Van Baak
tvb at LeapSecond.com
Mon Mar 30 23:32:50 UTC 2009
> Probably the higher jitter and periodic phase modulation due to
> simultaneous switching of multiple outputs at different frequencies.
> The magnitude of the latter will depend on the loads driven by each output.
> The cure is to use an external flipflop to resynchronise the outputs to
> the 10Mhz clock.
There was no phase modulation effect that I could measure.
Note that in that design all pins (a single 8-but IO port) are
re-written each time through the loop; not just ones that change.
See the source code for details.
My understanding of the PIC architecture is that all outputs
are essentially "resynchronized" to the clock by design. So
that's why the PIC divider works so well. I can't see how an
external off-chip flip-flop would be better than the existing
internal on-chip flip-flop. Might even make things worse?
But I don't know for sure and should not guess. In cases like
this I'd take an actual test over a random guess.
As for jitter, I tested the PIC divider when I wrote it ten years
ago and if I recall correctly the jitter was just over what I could
measure with a SR620; about 25 ps. With better equipment
these days, one could measure how much of that is input jitter,
or output jitter, or measurement system jitter. But I don't have
anything better than a 5370 or 620 for 1PPS measurements.
I know the PIC divider was an order of magnitude better than
other discrete 1PPS dividers that I had at the time, and it was
100x better than the reference 1PPS out of any GPS boards
that I had, so I was very pleased with the performance (and
the simplicity, and the cost) of the one-chip divider concept.
But it would be very interesting to me if someone with a working
Wavecrest could make measurements of various PIC dividers
and refine this old data; to find out just how low the noise floor is.
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