[time-nuts] fast freq. synthesis schemes
magnus at rubidium.dyndns.org
Wed Oct 14 20:48:28 UTC 2009
Bob Camp wrote:
> At least on paper you can run a DDS at VHF/UHF and put it into a (very)
> wideband PLL driving a 12-18 GHz VCO.
> As mentioned previously - spurs will be an issue. You also will need to get
> a hold of some DDS chips with GHz-ish clock rates.
One could use a suitably high frequency VCO or even YIG, locked to a DDS
and then use a suitable fixed oscillator for up-conversion. The PLL
locking would also use a DAC for VCO "bias" being updated at the same
time as the DDS. A look-up-table could be used for top DDS frequency to
bias conversion and a calibration round could be used to trim the table
up to minimize the bias-error. That way the VCO can be quick-jumped and
the PLL will immediatly steer the frequency back into lock. The PLL loop
thus only needs to handle error in bias-table, the remaining difference
in frequency and phase-relationship. Quite a different task than the
overall lock-range. An ADC for the non-biased value of the loop-filtered
detector would enable calibrations to be made automatic.
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