[time-nuts] Jitter Test on Dividers
bruce.griffiths at xtra.co.nz
Sun Sep 20 22:45:58 UTC 2009
Not surprising, given that there is typically about 30ns clock to output
delay per HC390 (divide by 2 and divide by 5 asynchronously cascaded)
with 7 asynchronously cascaded 390's between the 10MHz clock input and a
1PPS output having a typical total clock to output delay of 210ns with a
tempco of around 880ps/C. The observed variation could be produced by a
change of around 0.6C in the HC390 chip temperature.
John Miles wrote:
> Interesting! 500 picoseconds is a lot of drift. Can you try 74AC390s as
> -- john, KE5FX
>> -----Original Message-----
>> From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com]On
>> Behalf Of Brian Kirby
>> Sent: Sunday, September 20, 2009 2:19 PM
>> To: precise time
>> Subject: [time-nuts] Jitter Test on Dividers
>> I ran a 24 hour test on the async dividers (74HC390s) that Tom Clark
>> designed and they basically have a triangular peak to peak jitter of 500
>> picoseconds over 22 minutes. The baseline drift started at reference
>> 0 ns and made a negative parabola that dipped to -750 picoseconds
>> and then returned back to the reference, over 24 hours.
>> I check the TADD-2s (two units for seperate 12 hour test) and they
>> appeared to not have any drift. One unit showed a standard deviation
>> of 34 picoseconds, The other unit showed 20 picoseconds.
>> The time interval counter is a HP5370B, which tested at 20
>> picoseconds jitter.
>> Brian Kirby - KD4FM
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