[time-nuts] Jitter Test on Dividers

Magnus Danielson magnus at rubidium.dyndns.org
Sun Sep 20 23:11:37 UTC 2009

Bruce Griffiths wrote:
> Not surprising, given that there is typically about 30ns clock to output
> delay per HC390 (divide by 2 and divide by 5 asynchronously cascaded)
> with 7 asynchronously cascaded 390's between the 10MHz clock input and a
> 1PPS output having a typical total clock to output delay of 210ns with a
> tempco of around 880ps/C. The observed variation could be produced by a
> change of around 0.6C in the HC390 chip temperature.

Put the divider in a small box for isolation?


Regardless, the periodic wander needs to be traced to the phenomen.

A couple of students doing work at the company was quite supprised about 
the periodic noise they saw... that suddently stopped during a long 
measurement. Since I knew the house AC stopped running the fans at 18:00 
and it matched their stop an environmental effect was expected. Using a 
pair of strips of foam-tape over the oscillator (flimsy "Stratum 3") 
they removed the effect almost entierly. That a little tape and a few 
minutes of work could make such a difference was new to them. I think 
they learned something.


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