[time-nuts] OT: Practical PLL low noise?
lists at cq.nu
Tue Feb 2 17:30:10 UTC 2010
The first issue - your oscillator may be drifting quite a lot. If so, that's
the first thing to check and possibly fix. A reasonable oscillator should be
able to hold less than 100 Hz at 42 MHz under normal room conditions. Fixes
range from circuit improvements, to a better crystal, to simply eliminating
a draft that blows on the oscillator.
If the oscillator is reasonably stable, it will need to be turned into a
VCXO in order to lock it. If both oscillators use fundamental crystals, that
should not be very hard. If they use higher overtone crystals it may be more
of a challenge. Often you will find a tradeoff between good oscillator
performance and wide tuning range.
What ever chip you use to do the lock, keep the loop bandwidth small. The
GPSDO will be noisy and it will not help you for phase noise. I would start
the bandwidth at 100 Hz to be sure everything works ok and then start
narrowing it to 10 Hz or less. At some point the loop will be to narrow to
"keep up" with the changes and you will not be able to maintain phase lock.
What ever loop bandwidth you use, keep the phase margin large. You do not
need a fast locking loop. Instead you need one that has less tendency to
peak. Phase margins should be above 70 degrees.
The nice thing about doing this with a chip is that most of the
manufacturers have cute little web applications / free downloads to design
the loop filters for you. No digging out crazy formulas and wondering if you
got it all right.
Have fun !
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of francesco messineo
Sent: Tuesday, February 02, 2010 10:50 AM
To: Discussion of precise time and frequency measurement
Subject: [time-nuts] OT: Practical PLL low noise?
sorry for the OT, but I know there're many real electronic artists here.
As an amateur radio operator I often use transverters, some home made.
They usually can be made sigthly better (RF and noise-wise) than
japanese transceivers. However often the LO xtal oscillator drifts too
much for comfortable digital and weak signal work.
Now the big question: is there any PLL design that can lock 22 MHz and
42 MHz xtal oscillator to a 10 MHz reference (typically from a GPSDO)
without adding significant noise to the oscillators? The LOs usually
go to a single or doube balanced diode mixer like the famous
minicircuit ones, and at that point the RF signal has been already
amplified by 10 or 20 dB stage(s).
Other options would be "ovenizing" the LOs or making a DDS sinth.
Now, what would be more practical approach from the home construction point?
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