[time-nuts] OT: Practical PLL low noise?
francesco.messineo at gmail.com
Tue Feb 2 17:58:08 UTC 2010
On 2/2/10, Bob Camp <lists at cq.nu> wrote:
> The first issue - your oscillator may be drifting quite a lot. If so, that's
> the first thing to check and possibly fix. A reasonable oscillator should be
> able to hold less than 100 Hz at 42 MHz under normal room conditions. Fixes
> range from circuit improvements, to a better crystal, to simply eliminating
> a draft that blows on the oscillator.
it is drifting about 50 Hz during warm up, but the problem is thermal
drift internally as season changes, as tx/rx periods change, and so
> If the oscillator is reasonably stable, it will need to be turned into a
> VCXO in order to lock it. If both oscillators use fundamental crystals, that
> should not be very hard. If they use higher overtone crystals it may be more
> of a challenge. Often you will find a tradeoff between good oscillator
> performance and wide tuning range.
22 MHz can be fundamental, 42 MHz is third overtone for sure.
> What ever chip you use to do the lock, keep the loop bandwidth small. The
> GPSDO will be noisy and it will not help you for phase noise. I would start
> the bandwidth at 100 Hz to be sure everything works ok and then start
> narrowing it to 10 Hz or less. At some point the loop will be to narrow to
> "keep up" with the changes and you will not be able to maintain phase lock.
> What ever loop bandwidth you use, keep the phase margin large. You do not
> need a fast locking loop. Instead you need one that has less tendency to
> peak. Phase margins should be above 70 degrees.
> The nice thing about doing this with a chip is that most of the
> manufacturers have cute little web applications / free downloads to design
> the loop filters for you. No digging out crazy formulas and wondering if you
> got it all right.
thanks for the suggestions, any good candidate as a chip?
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