[time-nuts] CPLDs for clock dividers
dk4xp at arcor.de
Thu Feb 4 07:58:20 UTC 2010
Luis Cupido wrote:
> That is not by any means a CPLD. it is a big FPGA and I bet it would
> be doing a bazilon things besides the divider.
It shares the CPLD's problems of ground and VCC bounce. The Virtex
was completely empty otherwise and the counter was stoppable, so
it was easy to see the culprit.
Having a hundred ground pins should be more of an advantage and
wether the innards are fine-grained (FPGA) or sum-of-products-cells (CPLD)
really does not matter.
73s, Gerhard, DK4XP
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