[time-nuts] CPLDs for clock dividers

Bob Camp lists at cq.nu
Thu Feb 4 12:05:07 UTC 2010


One trick is indeed to turn all of the unused output pins into grounds. 

That does not help the power much. There you need good solid bypassing on all of the power pins. With a little CPLD you don't have many pins. WIth even a small FPGA there are a lot of them to bypass.  I've seen a number of boards where people have given up after fully bypassing most but not all of the power pins.


On Feb 4, 2010, at 2:58 AM, Gerhard Hoffmann wrote:

> Luis Cupido wrote:
>> That is not by any means a CPLD. it is a big FPGA and I bet it would
>> be doing a bazilon things besides the divider.
> It shares the CPLD's problems of ground and VCC bounce. The Virtex
> was completely empty otherwise and the counter was stoppable, so
> it was easy to see the culprit.
> Having a hundred ground  pins  should  be more of an advantage and
> wether the innards are fine-grained (FPGA) or sum-of-products-cells (CPLD)
> really does not matter.
> 73s, Gerhard, DK4XP
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