[time-nuts] CPLDs for clock dividers

Luis Cupido cupido at mail.ua.pt
Thu Feb 4 14:20:33 UTC 2010

I understand your arguments...

I just wonder why reality differs.
I had a design (GPSDO) that I tested on a FPGA
(Cyclone) and the same on MAXII and the difference
was abyssal !!!

Whatever... the MAXII family has a unbeatable jitter
performance compared to discrete logic... That I can tell
by direct observation. Other CPLD's I can't tell much
only MAX3000 that was slightly worst and MAX7000 that was
the same as TTL +/-. Know nothing about Xilinx or others...

There are so many devices nowadays that I do accept that we
may no longer set a guideline of what is good or bad in
general terms anymore.

Luis Cupido.

Gerhard Hoffmann wrote:
> Luis Cupido wrote:
>> That is not by any means a CPLD. it is a big FPGA and I bet it would
>> be doing a bazilon things besides the divider.
> It shares the CPLD's problems of ground and VCC bounce. The Virtex
> was completely empty otherwise and the counter was stoppable, so
> it was easy to see the culprit.
> Having a hundred ground  pins  should  be more of an advantage and
> wether the innards are fine-grained (FPGA) or sum-of-products-cells (CPLD)
> really does not matter.
> 73s, Gerhard, DK4XP
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