[time-nuts] Advice on 10 MHz isolation/distribution (Clay)

Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Feb 12 01:34:09 UTC 2010

life speed wrote:
> Message: 2
> Date: Fri, 12 Feb 2010 12:12:29 +1300
> From: Bruce Griffiths<bruce.griffiths at xtra.co.nz>
> The output (collectors of Q5, Q6 emitter of Q4) of the input amplifier
> sets the dc voltage at the inputs ( Q1 base, Q7 base respectively) of
> the output amplifiers.
> The circuit consists of a unity gain input amplifier (Q4, Q5, Q6) that
> drives a pair of output amplifiers (Q1, Q2, Q3 and Q7, Q8, Q9
> respectively) each with a gain of 2x (6dB).
> The input amplifier is essentially a white emitter follower with a
> complementary symmetry output stage (shown in transistor electronics
> books from the 1960's) where an input CE transistor drives a
> complementary pair of CE transistors with feedback from the common
> collectors of the 2 output transistors to the input transistor emitter.
> In effect its merely a very simple unity gain opamp. Its usually best to
> ensure that the CE output stage pair provide the dominant open loop
> pole. Using a higher ft (2 to 3x)  input transistor than the output pair
> is the usual way of ensuring this.
> Well, it is so obvious now that you explained it.  I had forgot about the need for one of the stages to set the dominant pole.
> Thanks Bruce and Bob for sharing your obsession with frequency controls.  I'll simulate this further, and have a prototype PCB built within the next few weeks.  I did notice the resistor at the base of Q2,5,8 is responsible for significant noise.  I'll have to be careful with the bias circuit.
> Have to get busy for now, but I will report back with results.
> Best regards,
> Clay

One can always use a smaller resistor in series with an RF choke that 
has no resonances in the region of interest.

The attached circuit schematic illustrates one method of biasing for 
which the emitter current of the input transistor can be largely sourced 
via a resistor rather than from the collector current of the npn output 

My simulations indicate if that one uses 2N3904's as the input device 
rather than the 2N5179's shown that there is an enormous peak in the 
output noise spectrum at around 150-200MHz or so.
When the 2N5179 is used this noise peak is much smaller and broader.

Use the same bias divider bypassing techniques that NIST used including 
the use of electrolytic caps (they used tantalum caps) to reduce the low 
frequency noise from the power supply. The ceramic bypass caps ensure 
sufficient isolation between stages.
Simulating the reverse isolation with realistic component parasitics is 
always informative/useful.

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