[time-nuts] Advice on 10 MHz isolation/distribution

Garry Thorp GThorp at pascall.co.uk
Fri Feb 19 15:17:44 UTC 2010

Hello Clay,
Joining in this discussion at a rather late stage  -  have you
considered using 74AC series gates as buffers? They provide reasonable
isolation and have surprisingly low phase noise.
A single 74AC04 inverter gives over 40dB reverse isolation at 10MHz, so
3 cascaded gates would give more than enough. You would need to use a
separate IC for each stage to achieve the isolation, but they are cheap!
With a series output resistor, a 74AC gate with 5V supply will give
~13dBm while providing a 50R source match. Adding a series tuned circuit
will give a sine wave if required. At 10MHz the first 2 stages will draw
~2mA and the output stage ~15mA (as a matched 50R source), so the
necessary isolation between power supplies can readily be achieved by
using separate RC filter chains to each IC.
I haven't measured the phase noise of an AC04, but I have tried dividing
a low-noise 100MHz OCXO using a 74AC163. At 100MHz, the OCXO's phase
noise was ~-80dBc/Hz at 1Hz offset, -110 at 10Hz, -140 at 100Hz, ~-166
at 1kHz and ~-180 at 10kHz and beyond.
Taking the Qc output of the AC163, the phase noise at 12.5MHz showed the
theoretical 18dB reduction at low offsets, i.e. ~-98 at 1Hz and -128 at
10Hz. It then went into a flicker of phase region, ~-155 at 100Hz and
-165 at 1kHz, reaching a floor of ~-178dBc/Hz by ~100kHz offset.
Extrapolating the flicker region downwards suggests the divider output
phase noise would be ~-145 at 10Hz and -135 at 1Hz. Intuitively, I
wouldn't expect an inverter to have worse phase noise than a counter
from the same family. Cascading 3 inverters would increase the flicker
phase noise by ~5dB, which I think would still be well within the spec
you gave earlier. This approach has the advantage that it can be done
without transformers or inductors (unless you need a sine wave output).
Digital inputs need a high slew rate to achieve low phase noise, so if
your oscillator has a sine wave output you would probably need to square
it up with a (non-saturating) limiter such as a common-base driving into
a Schottky diode limiter, or a long-tailed pair.
As CMOS is a saturating logic family, low-noise power supply is vital.
The input switching threshold is approximately half the supply voltage,
so supply noise + non-infinite slew rate = jitter. The lowest-noise LDO
regulators are probably not good enough. However this is a (relatively!)
straightforward low-frequency problem, that can be solved by using a
heavily filtered voltage reference with a low-noise op amp buffer or
Darlington emitter follower.
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