[time-nuts] 10MHz to 80MHz frequency multiplier suggestions
albertson.chris at gmail.com
Mon Jan 31 18:27:06 UTC 2011
I'd like to hear from one of the experts about which method has the
least noise a PLL or a multiplier. The PLL could have a very good
VCO, it could be a crystal oscillator that is steered by the phase
detector. The The multiplier could introduce noise in the mixers or
other active parts. I think the way to answer is to look at the
budget. At the $10 price point which is best? at $100 and at $1000?
I've seen it happen many times that the winning method changes with
budget mainly because of the characteristics of real world components.
I thought at first the 80Mhz might clock a sussession approximation
A/D while it sampled a value from a sample and hold. But if 80Mhz
sets the sample rate for an SDR then it is worth much more effect (and
cost) to get right.
I have an interest in this too as I'd like to drive a DDS chip with a
10Mhz GPSDXO and the DDS chips needs 100MHz clock and of course the
question is what is the best design at various price points
On Mon, Jan 31, 2011 at 9:48 AM, Elio Corbolante <eliocor at gmail.com> wrote:
> Chris Albertson wrote:
>> Does a A/D converter really need a GPS controlled clock?
>>In this case where exact precision is not required you could use a
>>4046 phase lock loop chip. You set the VCO for 80Mhz then divide that
>>by 8 and feed it back to the chip.[...]
>>If you go this route, I think the 80 Mhz signal will be good enough to
>>clock an A/D but maybe not for use as an 80Mhz precision frequency
> I'd prefer to multiply the clock because I'd like to have also a very low
> phase noise:
> the A/D is the one in the Perseus receiver (Direct sampling SDR receiver) <
> http://www.microtelecom.it/perseus/> and for measurement purposes I'd like
> to have it "spot on" frequency.
> As you can imagine, being for a receiver, the low phase noise is a
> _ Elio.
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