[time-nuts] Sine to LVDS
bruce.griffiths at xtra.co.nz
Fri Sep 9 19:16:26 UTC 2011
femtosecond jitter albeit with CMOS outputs.
This is difficult to achieve (especially at the lower end of its input
frequency range) with a comparator with 1ps of internal jitter.
A simple differential pair with the appropriate gain and bandwidth will
have somewhat lower jitter than a comparator, however as long as the
jitter is lower than that of the following logic achieving the lowest
possible output jitter from the sine to LVDS shaper may be somewhat
Since the input signal slew rate is so high a transformer with a centre
tap biased halfway between the LVDS input levels with a pair of inverse
parallel clamp diodes across the secondary plus a couple of low value
series resistors between the secondary and the clamp diodes should
suffice. Similar schemes are used by most of the high resolution
pipeline ADCs with sample clock frequencies of 50MHz or more.
These ADCs typically have sub picosecond sampling jitter.
However some LVDS receivers have built in attenuators to protect the
input so adding the diodes may not be required.
Luis Cupido wrote:
> I had similar need some time ago and
> I found that a differential pair with two (pnp) BFR93
> worked much better than any comparator(three or four tested, but not
> the adcmp604).
> (was a pll reference and I judged the impact of such
> observing the phase noise at microwaves).
> On 9/9/2011 12:29 PM, Javier Herrero wrote:
>> Thanks for the reminder :)
>> Te available 180MHz signal has that level, and it is quite heavily
>> bandpass filtered, since it comes from a multiplier chain from an 45MHz
>> OCXO, so the ADCMP604 will fit nicely
>> Best regards,
>> El 09/09/2011 13:07, Bruce Griffiths escribió:
>>> Javier Herrero wrote:
>>>> Hello all,
>>>> I think that the same question that has been discuted here a zillion
>>>> times but usually around 10MHz... anyway, what would be the best way
>>>> to convert a sine wave to a LVDS clock (preferably duty cycle 50%) at
>>>> Texas Instruments suggest a LVDS receiver as a comparator
>>>> http://www.ti.com/lit/an/slyt180/slyt180.pdf but time ago this was
>>>> discussed here, and not very favoured due to the high hysteresis of
>>>> the LVDS receivers.
>>> Use a true LVDS comparator (e.g. ADCMP604).
>>> With 1:1 transformer coupled input and a pair of inverse parallel
>>> schottky diodes across the inputs together with series resistors
>>> between the transformer secondary to the comparator inputs should
>>> suffice for inputs of +16dBm or more.
>>> With sufficient input from a low noise source a cycle to cycle jitter
>>> of 1-2ps should be feasible.
>>> Sub picosecond jitter is feasible if one cascades a series of low pass
>>> filtered limiter stages.
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