[time-nuts] Sine to LVDS

Javier Herrero jherrero at hvsistemas.es
Fri Sep 9 19:46:23 UTC 2011

El 09/09/2011 21:16, Bruce Griffiths escribió:
> Since the input signal slew rate is so high a transformer with a 
> centre tap biased halfway between the LVDS input levels with a pair of 
> inverse parallel clamp diodes across the secondary plus a couple of 
> low value series resistors between the secondary and the clamp diodes 
> should suffice. Similar schemes are used by most of the high 
> resolution pipeline ADCs with sample clock frequencies of 50MHz or more.
> These ADCs typically have sub picosecond sampling jitter.
> However some LVDS receivers have built in attenuators to protect the 
> input so adding the diodes may not be required.
I will do something like that. In fact, the LVDS clock output will not 
be single (I need to provide them to three different systems, only one 
of them under my further resposibility), and I was thinking on get first 
one LVDS output from the ADCMP604 and fed it to a clock distribution IC. 
1-2ps period to period jitter is enough (in fact, 1-2ps jitter exceeds 
my current measurement capabilities, but this is another history :) ). 
For now I've not a specific jitter requirement, but from final 
application requirements, it would be around that level.

Thanks! Best regards,


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