[time-nuts] PICTIC II ready-made?

[EWKehren at aol.com]

correct
Bert Kehren
 
 
 
In a message dated 4/27/2012 6:58:32 P.M. Eastern Daylight Time,  
azelio.boriani at screen.it writes:

FPGA  with internal flash memory to boot from, yes, but I think that small
CPLD  haven't to boot anything: they should have the interconnection  array
associated with the EEPROM cell array.

On Fri, Apr 27, 2012 at  11:52 PM, David <davidwhess at gmail.com> wrote:

> On Fri, 27 Apr  2012 22:13:55 +0200, Azelio Boriani
> <azelio.boriani at screen.it>  wrote:
>
> >By "preload" I think you mean the configuration  step of the logic. It
> seems
> >that the Xilinx one stops the  clock after the configuration is done.
> Anyway
> >using small  EEPROM based CPLDs you have no clock at all: there is no
>  >configuration to load.
>
> Wouldn't that also apply to an  EEPROM based FPGA?  I have been
> thinking that SRAM based devices  may be a better match in cases where
> you only want to have to program  one device.
>
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