[time-nuts] GPSDO Alternatives

SAIDJACK at aol.com SAIDJACK at aol.com
Fri Dec 7 07:12:22 UTC 2012

metastability is not an issue in this type of application, nor can it be  
avoided since we have two different clock domains.
It would only shift the capture point by one counter clock cycle back or  
forth if the edge happens right on the transition point. At that  point we 
have 50% uncertainty where it should fall anyway's, so the  best one could do 
is switch back and forth between the two counter values  creating an average 
of half way between these two counter points!
Also the GPS sawtooth will create enough jitter on the  capture pin to 
avoid staying in metastability for more than one  pulse.
Metastability is an issue for applications that need to be bit-accurate,  
such as trying to capture a serial datastream etc. A 1PPS capture application 
in  a GPSDO is not a bit-accurate affair, it is a heavily averaged (low 
pass  filtered) system so statistics kick in.
The real problem of the LPC932 capture system is that the resolution goes  
from 33ns on the counter to something around 200ns because of the pin 
clocking  the input FF at 5MHz... its a waste of possible resolution on that chip. 
 200ns is quite a low resolution for a GPSDO, but there are ways to improve 
this  resolution through dithering for example.
In a message dated 12/6/2012 20:35:35 Pacific Standard Time,  
hmurray at megapathdsl.net writes:

SAIDJACK at aol.com said:
> Then setting up a test system we  noted that the timer can capture with
> 32MHz resolution which is good  enough for a low-cost GPSDO 
> but that they gated the  input pin through a flip-flop running at CPU core
> speed, which was  around 6MHz if I remember correctly. 

davidwhess at gmail.com  said:
> The ATmega328 apparently has something similar going on since  the 
> says that the maximum external asynchronous clock  frequency is 1/4 of the
> CPU frequency.  That is why I suggested  synchronously clocking the CPU
> directly from the OCXO.  Atmel's  datasheet is annoyingly vague about some
> matters and I assume the  capture input works like it should. 

You have to do something  appropriate when multiple clocks are involved or 
get metastability  issues.

I think the 1/4 limit is to allow the external pin to be used  to clock the 
counter.  If you run the external signal through the  standard pair of FFs 
get a signal that is synchronous to your clock,  1/4 guarantees that you 
see all transitions.  At 1/2, with the  duty cycle slightly off 50-50, you 
might end up with hanging-bridge type  cases where the output of the 
synchronizer always sees the same  level.

Actually, metastability is hard to hit.  Most  "metastability" issues are 
really just setup/hold  bugs.

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