[time-nuts] Questions about TAC frontend, and some measurements
lists at rtty.us
Sun Dec 23 04:10:29 UTC 2012
One very simple question - how good would it do if you just did it all with logic gates? Tri-state buffers and things like that….
Now that you are up to a 100 to 200 ns long pulse, a lot of the fiddly stuff about "can't get a 2 ns pulse through it" goes away.
I'm not suggesting you tear up what you have. It's just something else to try and compare.
On Dec 22, 2012, at 6:00 PM, Fabio Eboli <fabioeb at quipo.it> wrote:
> Hello, Bruce
>> Using saturated transistors as switches in the current source and
>> elsewhere isn't conducive to fast switching.
>> The traditional arrangement using current mode switches is much
>> faster and more predictable.
> This is something I'd like to understand better.
> I'm referring to this schematic here:
> Q2 and Q5 are saturating toward the end of the
> ramp pulse, when the ramp capacitor C1 starts
> to go up.
> I was prepared to see the circuit I designed
> fail miserably on switch time, but it seem
> to be working, as far as I could see on the DSO.
> As far I can understand, the fact that Q2 and Q6
> don't saturate, saves the circuit, since
> at the end of the ramp, when Q1 and Q5 are
> into saturation, Q6 is able to steer the
> current to ground, and reverse bias BE (and CB)
> of Q5. Is this correct, or I was only
> lucky with the specific parts I used?
>> Buffering the ramp with an opamp requires that the opamp settling
>> time be known so that the opamp has fully settled before a sample is
>> taken. With a charge redistribution ADC that has a sampling switch
>> connected to a capacitor array a buffer isnt usually necessary.
> I was planning to read the voltage with a microcontroller's ADC.
> I will set a fixed delay from the PPS rising edge and start
> sampling there. To do so I need that the voltage on integrating
> capacitor to stay reasonably stable during the delay.
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