[time-nuts] Questions about TAC frontend, and some measurements
bruce.griffiths at xtra.co.nz
Sun Dec 23 06:42:13 UTC 2012
Fabio Eboli wrote:
> Hello, Bruce
>> Using saturated transistors as switches in the current source and
>> elsewhere isn't conducive to fast switching.
>> The traditional arrangement using current mode switches is much
>> faster and more predictable.
> This is something I'd like to understand better.
> I'm referring to this schematic here:
> Q2 and Q5 are saturating toward the end of the
> ramp pulse, when the ramp capacitor C1 starts
> to go up.
> I was prepared to see the circuit I designed
> fail miserably on switch time, but it seem
> to be working, as far as I could see on the DSO.
> As far I can understand, the fact that Q2 and Q6
> don't saturate, saves the circuit, since
> at the end of the ramp, when Q1 and Q5 are
> into saturation, Q6 is able to steer the
> current to ground, and reverse bias BE (and CB)
> of Q5. Is this correct, or I was only
> lucky with the specific parts I used?
>> Buffering the ramp with an opamp requires that the opamp settling
>> time be known so that the opamp has fully settled before a sample is
>> taken. With a charge redistribution ADC that has a sampling switch
>> connected to a capacitor array a buffer isnt usually necessary.
> I was planning to read the voltage with a microcontroller's ADC.
> I will set a fixed delay from the PPS rising edge and start
> sampling there. To do so I need that the voltage on integrating
> capacitor to stay reasonably stable during the delay.
The classic TAC using current mode switching is similar to the attached
The reset circuit uses a pair of matched diodes with nominally equal
currents flowing in them to ensure a controlled reset with low offset.
The enhanced current sources improve the current source output impedance
over that of a simple current source.
Opamps can be used to improve the current source accuracy however
maintaining the current source output impedance at high frequencies can
then be problematic if suitable decoupling of the opamp from the current
source emitter and base isnt used.
Only the sampling jitter is significant in that combined with the
leakage current in hold mode it is equivalent to a much smaller timing
jitter at the input.
For example a 1uA leakage current in hold mode combined with a 10mA
charging current is equivalent to 100ps of TAC input jitter.
Using faster lower capacitance transistors is helpful in reducing
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