[time-nuts] 2.5 Ghz 12 digit counter project
ewkehren at aol.com
Fri Dec 28 13:38:18 UTC 2012
Lets call it what it is waste of time and money
Sent from Samsung tabletBob Camp <lists at rtty.us> wrote:Hi
As far as I can see, you would do *much* better with a surplus HP counter (sub $200 or even sub $100) and some sort of pre-scaler.
On Dec 28, 2012, at 2:51 AM, Bruce Griffiths <bruce.griffiths at xtra.co.nz> wrote:
> Tom Harris wrote:
>> Watch out for Silicon Chip designs, they have a habit of not making the
>> source code available, which you only find out at the end of the project. I
>> suppose that it is to allow the author to make a few extra $$ selling
>> programmed micros. They had a nice 3 phase inverter design a year ago that
>> had this problem, I wrote to the author promising not to distribute the
>> source, I just wanted to read it, but didn't even get the courtesy of an
>> I suspect that this counter is like the inverter, an oldish design that is
>> not worth building as you can get the same for half the cost out of China.
>> What makes it worthwhile is getting the hardware& the source code, so that
>> you can tinker with it.
>> Actually I had a look at the counter and it looks similar to the 8 digit
>> designs using the Intersil 7217 IC from the 80's.
>> Gripe ends.
>> On 28 December 2012 06:12, Paul Amaranth<Paul at auroragrp.com> wrote:
>>> Did anyone see the article in the December Silicon Chips magazine about
>>> building a 12 digit 2.5 GHz counter? It has an option for a GPS 1pps
>>> input so you could have some expectation that the last couple of
>>> digits mean something. The website only has the article cover page
>>> in pretty much unreadable type.
>>> Paul Amaranth, GCIH | Rochester MI, USA
>>> Aurora Group, Inc. | Security, Systems& Software
>>> paul at AuroraGrp.Com | Unix& Windows
>>> time-nuts mailing list -- time-nuts at febo.com
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> I've read the entire set of articles and like most of the designs from this particular designer its largely an unadulterated piece of junk.
> Aside from the usual logic design errors I've come to expect from this designer the GPS PPS input is used directly to set the gate time so jitter on this signal directly (several tens of nanaosec or even more if sawtooth error is present better if the PPS is derived from a GPSDO) affects accuracy.
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